This invention relates generally to automatic test equipment, and more particularly to extending synchronous busses in automatic test systems that test synchronous bus devices.
Modern computer systems employ high-speed synchronous busses for communicating data. Synchronous busses coordinate operations on a bus by providing a common clock to all bus devices. Asynchronous busses do not use a common clock to coordinate activities. Examples of synchronous busses include PCI, AGP, and Cardbus.
Manufacturers of electronic circuit boards employ automatic test equipment (xe2x80x9cATExe2x80x9d or xe2x80x9ctestersxe2x80x9d) to ensure that their products meet requirements for performance and functionality. In one testing configuration, a unit under test (xe2x80x9cUUTxe2x80x9d) is attached to a tester via one or more interface connectors, and the tester exercises the UUT by reproducing the UUT""s native environment. Where the UUT is itself a synchronous bus card, a tester might reproduce the bus environment by including a complete synchronous bus to which the UUT connects.
Certain characteristics of synchronous busses make ATE testing of synchronous bus cards problematic. A primary limitation of synchronous busses is that in order to operate at high speed they must generally be kept short. Synchronous busses that operate at 33 MHz and above are seldom more than one foot long. The need to keep synchronous busses short forces the entire bus with all of its accompanying hardware and cooling into a location near the tester interface. The area around the tester interface tends to be crowded already, however. In addition to being the focal point of most of the tester""s resources, the tester interface typically also includes test adapters, auxiliary equipment, and handlers for loading and unloading UUTs. Therefore, the need to keep synchronous busses short conflicts with the lack of available space near the tester interface.
Synchronous busses also tend to suffer from poor fault isolation. Defects on one card can appear as failures on other cards, and can cause an entire bus to malfunction. A benchmark of successful ATE is the ability to isolate faults. The lack of fault isolation common to most synchronous busses directly conflicts with the need for high fault isolation in ATE.
Some synchronous busses support changing bus cards with power applied, and can identify a new card xe2x80x9clivexe2x80x9d without requiring an explicit reset (a feature known as xe2x80x9chotswappingxe2x80x9d). Many busses are not set up to allow cards to be quickly changed, however. These busses must be powered down before a card can be inserted or removed, and a time-consuming reset must be performed before normal operation can resume. ATE systems typically test a large volume of cards in assembly-line fashion. For busses that do not support hot-swapping, the time-consuming procedure for swapping cards conflicts with the ATE requirement of high throughput.
FIG. 1 illustrates a synchronous bus of the type that is commonly used in modern computer systems, and illustrates the need for synchronous busses to be kept short. Clock driver 112 buffers a master clock signal 114 and provides an individual version of the master clock to each clock receiver 120 on each device 122, 124, and 126 plugged into the bus 110. The clock driver 112 distributes the master clock signal 114 to all slots on the bus with nearly zero timing skew: that is, nearly zero phase difference appears between the clock signals on the different slots of the bus.
As shown in FIG. 1, each device 122, 124, and 126 on the bus 110 includes a data transmitter 116, a data receiver 118, and a clock receiver 120. The bus 110 is arranged in a multi-drop, multi-master configuration, in which any device can transmit or receive data from any other device on the bus. For example, device 122 can transmit data signals using its transmitter 116 to device 126, and device 126 can then receive the data signals using its receiver 120.
FIG. 1 identifies xe2x80x9cTpropxe2x80x9d as the time required for data signals to travel down the bus and settle. Tprop is a finite delay related to a number of factors, including the bus"" physical length, its impedance, the impedance of devices on the bus, inductive and capacitive loading, and bus terminations. If the period of the master clock 114 is much longer than Tprop, data signals from device 122 have adequate time to travel down the bus and settle at device 126 before the next clock edge. If Tprop approaches or exceeds the clock period, however, device 126 receives its clock edge before the data signals settle, and invalid clocking can occur. For proper operation, Tprop must always be less than the clock period. The practical result of the requirement that Tprop be less than the clock period is that very fast synchronous busses tend also to be very short.
Various techniques have been used to extend the length of synchronous busses, with partial success. These techniques include changing bus loading, slowing down the bus, bridging, and remote bus control.
Delay time Tprop depends not only upon a bus"" physical length, but also upon its electrical loading. By reducing bus loading, it may be possible to physically extend a bus and still keep Tprop shorter than the clock period.
As a practical matter, reducing bus loading produces only small gains. Most bus implementations aggressively control bus loading, and leave little margin for improvement. Under the best conditions, reducing bus loading allows synchronous busses to be extended only a few inches. In an ATE environment, this improvement is too small to be useful.
As the clock period of a bus limits its maximum length, one can theoretically lengthen a bus by slowing its clock period. The longer the clock period, the further data can travel before false clocking occurs.
Slowing the clock period seems to be a simple and attractive way of extending a bus, but this technique has several drawbacks. First, not all busses allow their clock periods to be changed. Second, running a bus at reduced speed slows operations on the bus, and can reduce the throughput of an entire system. Third, extending a bus adds loading to the bus and can cause ringing in the clock signal, which ringing itself can cause false clocking. Reducing the clock period does not reduce the ringing. In some circumstances, however, slowing the edges of the clock does reduce ringing. Slowing clock edges is difficult to achieve in practice, however. Last, testing UUTs at reduced speed can fail to reveal certain types of defects. Many faults manifest themselves only when a UUT is operated at its rated speed. Slowing the clock sacrifices fault detection, and thus conflicts with a primary purpose of ATE.
FIG. 2 illustrates bus bridging, a commercially available technique for extending synchronous busses. One product that appears to provide a form of bus bridging is the model 2130 available from SBS Technologies, Inc., St. Paul, Minn. As shown in FIG. 2, a bridge device 218 straddles an original synchronous bus 210 and an extended synchronous bus 212. The bridge device 218 copies signals between busses 210 and 212 and allows a remote device 216 to communicate back and forth with a local device 214. Bridging effectively connects busses in series while electrically isolating the busses from each other. Multiple bridge devices can be cascaded to extend a bus even further.
Each bus segment that forms part of a bridged configuration must conform to the specification of the bus for maximum length. Thus, bridging allows busses to be cascaded, but does not extend the length of any individual bus segment. Therefore, bridging does not address the need to keep the area around the UUT clear.
Remote bus control has been used to extend synchronous busses by long distances. One product that appears to provide a form of remote bus control is the model TA300 from Catalyst Enterprises, Inc., San Jose, Calif. Remote bus control operates by translating bus signals into a different bus protocol, transmitting the translated signals to a remote location, and translating the signals back to their original form to reconstruct the bus signals at the remote location.
FIG. 3 illustrates an example of remote bus control. A controlling device 314 on a local synchronous bus 310 communicates with a remote device 320 on a remote synchronous bus 312. The busses communicate using a local translating device 316 that plugs into the local synchronous bus 310, a remote translating device 318 that plugs into the remote bus 312, and an interconnection 322 between the two translating devices. In certain implementations, the remote bus 312 is omitted, and the remote device 320 plugs directly into the translating device 318.
Remote bus control is almost infinitely extendable, but it suffers from many disadvantages, particularly in ATE. First, remote bus control tends to be costly because it requires a significant amount of hardware and software to accomplish its control. Second, remote bus control does not communicate with the remote card using the remote card""s native environment. Remote bus control requires translation into a different protocol, for example a serial bus protocol, suitable for long-distance transmission. Remote bus control does not use the remote card""s native xe2x80x9cdevice driver.xe2x80x9d A xe2x80x9cdevice driverxe2x80x9d is a program that manages communication between the operating system of a host computer and a device. Remote bus control inserts a different bus protocol between the operating system and the device and does not use the native device driver to exercise the remote card. Third, remote bus control requires the use of hardware near the UUT. Even if the remote bus 312 is eliminated, the translating device 318 still is located near the UUT.
With the foregoing background in mind, it is an object of the invention to extend a synchronous bus an arbitrarily long distance using the bus"" native bus protocol.
Another object of the invention is to allow hot swapping of remote bus cards, regardless of whether the bus normally supports hot swapping.
It is yet a further object to prevent faults on the remote bus card from causing faults to occur in other locations of a system, and therefore to promote fault isolation.
To achieve the foregoing objects and other objectives and advantages, a method of extending a synchronous bus uses an extender device that physically engages the synchronous bus. The method includes receiving a plurality of bus signals from the synchronous bus, driving the plurality of bus signals to a remote device via an interconnect, and receiving return signals from the remote device over the interconnect. The method further includes establishing a hold-off interval, at least as long as the settling time of the return signals, and applying the return signals to the synchronous bus after the hold-off interval elapses.
In accordance with another aspect of the invention, a method of extending a synchronous bus using an extender device that physically engages the synchronous bus includes monitoring the synchronous bus to detect a transaction with a remote device. The transaction includes contents that encode a configuration of the remote device. The method further includes storing the contents of the transaction with the remote device, to maintain a local copy of the configuration of the remote device.
In accordance with another aspect of the invention, a method of testing UUTs includes building a record of configuration data for a first UUT. The method also includes blocking a flow of power between the synchronous bus and the first UUT until a time after a second UUT is installed. The method includes copying the record of configuration data for the first UUT onto the second UUT before proceeding to test the second UUT. The method thereby allows UUTs to be exchanged safely while the synchronous bus remains operative.
In accordance with another aspect of the invention, a bus extender for extending a synchronous bus facilitates the testing of synchronous bus cards. The bus extender includes an extender device, coupled to the synchronous bus, and an interconnect, coupled to the extender device and extending over a length to a connector arranged to engage a UUT. The extender device includes a hold-off circuit, coupled to the interconnect and the synchronous bus. The hold-off circuit includes a delay register for storing a hold-off interval, based upon the length of the interconnect, and a delay circuit. The delay circuit prevents return signals that arrive from the UUT from asserting onto the synchronous bus until the hold-off interval elapses.
Additional objects, advantages and novel features of the invention will become apparent from a consideration of the ensuing description and drawings.